The invention relates to a semiconductor memory device, and especially to a semiconductor memory device in which a defective memory cell is replaced with a redundant memory cell array when a defective part occurs in a main memory and information on an address of a defective memory cell is generated by selectively disconnecting fuses.
In a semiconductor memory device, it sometimes occurs that a memory cell array does not operate because it is used exceeding a margin determined at the time of designing or fabrication, or fabricated imperfectly. If there is a part which does not operate as mentioned in the above, the whole semiconductor memory device may be regarded as inferior goods.
Hitherto, a defective memory cell array is replaced with a redundant memory cell array prepared previously on the basis of information on an address of the defective memory cell which is obtained in a test performed before the semiconductor memory is packaged. When the defective memory cell array is replaced with the redundant memory array, information on the address of the defective memory cell is generated by selectively disconnecting fuses. In case that the defective memory cell array is replaced with the redundant memory cell array, the address of the defective memory cell is assigned to that of the redundant memory cell array on the basis of information on the address of the defective memory cell. Accordingly, when an address signal corresponding to the defective memory cell is inputted, the memory cell of the redundant memory cell array is selected, and the semiconductor memory device is kept to be used as an excellent article though there is a defective part therein.
FIG. 1 shows a conventional semiconductor memory device. Although a single redundant circuit is shown in FIG. 1, the number of the redundant circuits is the same as that of the redundant memory cell arrays in the actual semiconductor memory device.
The semiconductor memory device shown in FIG. 1 is composed of a constant current-generating unit 1, latches 20A, 20B, 20C, 20D, 20E, 20F, P-type MOS transistors 30, 31, 32, 33, 34, 35, fuses (Fus) 40, 41, 42, 43, 44, 45, transfer gates (TGs) 50, 51, 52, 53, 54, 55 and an inverter 60. Although a single fuse block corresponding to a single memory cell array is shown in FIG. 1, the plural fuse blocks are provided in accordance with the number of the memory cell arrays in the actual semiconductor memory device. Moreover, the memory cell array is omitted in FIG. 1.
The constant current-generating unit 10 is composed of an inverter 11 for inverting a reset signal Sr, a N-type MOS transistor 12 operating in accordance with an output signal of the inverter 11, a P-type MOS transistor 13 inserted between the N-type MOS transistor 12 and a power supply VDD, a P-type MOS transistor 14 inserted between the power supply VDD and a gate of the P-type MOS transistor 13, and a resistor 15 connected with a source of the N-type MOS transistor 12 and the ground GND. The gate of the P-type MOS transistor 13 is connected with the drain of the N-type MOS transistor 12.
Since structures of the latches 20A to 20F are the same, only the structure of the latch 20 A will be explained here, and explanations on those of the other latches will be omitted. The latch 20A is composed of a transfer gate 21 and inverters 22, 23. In the transfer gate 21, the inverter 22 is inserted between a terminal A and an output terminal of FOS, an inverter 23 is inserted between a terminal B and the output terminal of FOS, a terminal C is connected with a terminal 70, and a terminal C bar is connected with an output terminal of the inverter 60 and a terminal C of the transfer gate 50. The fuse information FOS is outputted from the latch 20A. Fuse disconnection informations F01 to F05 for specifying addresses of defective memory cells in the main memory cell array are respectively outputted from the latches 20B to 20F. In the transfer gate 50, a terminal C bar is connected with the terminal 70, a terminal A is connected with a terminal of the fuse 40 on the side of a high potential, and a terminal B is connected with an input terminal of the inverter 23. The fuse 40 is provided to generate the fuse information FOS for deciding whether the redundant circuit is used or not.
Gates of the P-type MOS transistors 30 to 35 are connected with an output terminal (a FC signal-output terminal) of the constant current-generating unit 10, sources of the same are respectively connected with the power supply VDD, and drains of the same are respectively connected with the fuses 40 to 45. The other terminals of the fuses 40 to 45 commonly connected with the ground GND.
FIG. 2 explains operations of important structural elements shown in FIG. 1. FIG. 3 explains an operation of the constant current-generating unit 10. An operation of the semiconductor memory device shown in FIG. 1 will be explained referring to FIGS. 1, 2, and 3.
In an ordinary state, the high logical level is applied to the terminal 70. Accordingly, the low logical level is applied to the N-type MOS transistor 12 via the inverter 11 in the constant current-generating unit 10. Then, the N-type MOS transistor 12 turns off, and the P-type MOS transistor 14 turns on. Since the P-type MOS transistor 14 turns on, a terminal 71 is precharged by the power supply VDD, and the P-type MOS transistor 13 turns off. Accordingly, the P-type MOS transistor 30 to 35 turn off, and a current flows through none of the fuses 40 to 45, and terminal voltages of the fuses 40 to 45 which are respectively denoted by FMS, FM1 to FM5 are at uncertain levels.
At this time, in each of the transfer gates 50 to 55, since the low logical level is applied to the terminal C via the inverter 60 and the high logical level is applied to the terminal C bar from the terminal 70, each of the transfer gates 50 to 55 turns off. On the other hand, in the transfer gate 21 of each of the latches 20 A to 20F, since the high logical level is applied to the terminal C from the terminal 70 and the low logical level is applied to the terminal C bar via the inverter 60, the transfer gate 21 turns on.
Next, a case that a reset signal Sr is inputted to the terminal 70 when the memory is initialized will be explained. The reset signal Sr changes into the low logical level in one-shot.
Since the reset signal Sr inputted to the terminal 70 is inverted by the inverter 11 in the constant current-generating unit 10 and inputted to the gate of the N-type MOS transistor 12, the N-type MOS transistor 12 and the P-type MOS transistor 13 turn on, and the P-type MOS transistor 14 turns off. As a result, a voltage at a certain level is impressed upon the terminal 71 as the FC signal, and the P-type MOS transistors 30 to 35 turn on simultaneously, since the fuses 40 to 45 are respectively connected with the P-type MOS transistors 30 to 35, a fuse current flow in case that the fuse is connected and does not flow in case that the fuse is disconnected. A voltage is generated between the terminals of the fuse 40, 41, . . . , or 45 in case that the fuse current does not flow. That is to say, whether the fuse is disconnected or not can be discriminated on the basis of the terminal voltage of the fuse as shown in FIG. 2.
At this time, in each of the transfer gates 50 to 55, the reset signal Sr at the low logical level is applied to the terminal C bar, and the high logical level, which is derived by inverting the reset signal Sr by the inverter 60, is applied to the terminal C. Accordingly, each of the transfer gates 50 to 55 turns on, and an input signal supplied to the terminal A is transmitted to the terminal B straightly. For instance, if the fuse 40 is disconnected since the terminal voltage FMS of the fuse 40 is at the high logical level, the voltage impressed upon the terminal A of the transfer gate 50 (the high logical level) is transmitted to the terminal B of the transfer gate 50, and inverted by the inverter 23, hence a voltage at the low logical level is outputted as FOS. Moreover, if the fuse 40 is connected a voltage at the low logical level is generated at the terminal of the fuse 40 on the side of VDD as FMS. This signal is outputted to the terminal B of the transfer gate 50, and inverted by the inverter 23 to change into the high logical level. Similarly, the transfer gates 51 to 55 connected with the fuses 41 to 45 respectively turn on, and the signals F01 to F05 (the address informations of the defective cells) are respectively generated in accordance with the disconnections of the fuses.
If the reset signal Sr is at the low logical level and the output of the inverter 23 (FOS) is at the low logical level, the fuse 40 is disconnected. In this case, the output of the inverter is inverted by the inverter 22, and inputted to the terminal A of the transfer gate 21. At this time, the output of the inverter 60 is at the high logical level, and inputted to the terminal C bar. Moreover, since the reset signal Sr is at the low logical level, the transfer gate 21 turns off.
However, if the reset signal Sr at the terminal 70 changes into the high logical level, since the high logical level is applied to the terminal C of the transfer gate 21 and the low logical level is applied to the terminal C bar of the transfer gate 21, the signal supplied from the inverter 22 (the high logical level) passes through the transfer gate 21. The output of the transfer gate 21 is inverted by the inverter 23 to change into the low logical level, and again changes into the high logical level in the inverter 22. Since the signal circulates through a loop represented as the inverter 22, the transfer gate 21, the inverter 23, the inverter 22 and so on, the fuse information is latched by the loop.
However, according to the conventional semiconductor memory device mentioned in the above, since the fuses connected with the P-type MOS transistors in series are situated between the power supply VDD and the ground, the current flowing through the fuses become high, because the resistance of each fuse is nearly the same as that of an ordinary conductive wire. The number of the fuses becomes large as the capacity of the memory device is large, and the total fuse currents become high. Since flip-flops in the semiconductor memory device are initialized collectively when the memory is initialized in most cases, the consumed currents at the time of initialization become high as the capacity of the memory is large.
The semiconductor memory devices in which the currents flowing through the fuses are reduced are disclosed in Japanese Patent Applications Laid-open Nos. 63-217600,2-161698, and 11-168143. In the semiconductor memory device disclosed in Japanese Patent Application Laid-open No.63-217600, a pulse signal for notifying a fuse information is generated synchronizing with turning-on of a power supply, and a fuse is judged disconnected from xe2x80x9c1xe2x80x9d level of the fuse information and connected from xe2x80x9c0xe2x80x9d level of the fuse information, hence a fuse current is reduced. In the semiconductor memory device disclosed in Japanese Patent Applications Laid-open No. 2-161698, the fuses are provided for the redundant circuits, and the thereby the currents do not flow through the fuses. In the semiconductor memory device disclosed in Japanese Patent Laid-open No.11-168143, the first fuse is disconnected in case that the redundant circuit is not used, and the second fuse is disconnected in case that the redundant circuit is used, hence the fuses currents are reduced.
However, in the semiconductor memory device disclosed in Japanese Patent Application Laid-open No.63-217600, it is necessary to provide a power supply-initializing circuit for generating a fuse signal. In the semiconductor memory device disclosed in Japanese Patent Application Laid-open No.2-161698, it is necessary to provide a redundant address-setting circuit in addition to a fuse circuit, and the fuses are provided for the redundant address-setting circuit. In the semiconductor memory device disclosed in Japanese patent Applications Laid-open No.11-168143, plural fuses are used in order to obtain a single fuse information. As mentioned in the above, the methods used in the aforementioned conventional semiconductor memory devices cannot be applied to the circuit structure shown in FIG. 1 in order to reduce the fuse currents.
Accordingly, it is an object of the invention to provide a semiconductor memory device in which peripheral circuits of fuses of an unused redundant circuit are not initialized and consumed currents are reduced in case that the peripheral circuits of fuses are initialized.
According to the feature of the invention, a semiconductor memory device comprises a main memory, redundant memory cell arrays, and redundant circuits, each of which replaces a defective memory cell with the redundant memory cell array and assigns an address of the defective memory cell on a basis of disconnections of plural fuses when a defective part occurs in the main memory, wherein each of the redundant circuits comprises:
a fuse block which assigns the address of the defective memory cell by selectively disconnecting the plural fuses,
plural address-generating latches which individually generate and hold fuse informations, each being represented as a binary data, depending on whether a current flows through at least one of the plural fuses or not, when the main memory is initialized,
a redundant circuit-selecting latches which is provided with a redundant circuit-selecting fuse to be disconnected in case that the redundant circuit is used, generates and holds a fuse information represented as binary data depending on whether a current flows through a redundant circuit-selecting fuse or not, when the main memory is initialized, and generates a signal for notifying disconnection of a fuse in case that the redundant circuit-selecting fuse is disconnected, and
a semiconductor switch which forms a returning path of the current flowing through the at least one of the plural fuses responding to the signal for notifying the disconnection of the redundant circuit-selecting fuse.
According to the aforementioned structure, if the redundant circuit-selecting fuse is disconnected, the redundant circuit-selecting latch outputs a signal notifying that the redundant circuit-selecting fuse is disconnected to the semiconductor switch. When the signal notifying the disconnection of the redundant circuit-selecting fuse is inputted to the semiconductor switch the semiconductor switch connects all the fuses in the plural address-generating latches with the ground so that the returning paths of the fuse currents are formed. At this time, the plural address-generating latches generated and hold the different fuse informations depending on whether the fuses are disconnected or connected. The fuses in the address-generating latches are supplied with the currents only in case that the redundant circuit-selecting fuse belonging to the same group is disconnected in other words the redundant circuit is used, and the currents do not flow through the fuses of the unused redundant circuit. Accordingly, in the above mentioned structure in which information on disconnections of the fuses is judged and latched on the basis of the fuse currents at the time of initialization, the fuse currents at the time of initialization can be reduced.